Buried digit spacer separated capacitor array

ABSTRACT

The present invention relates to the field of semiconductor integrated circuits and, in particular, to capacitor arrays formed over the bit line of an integrated circuit substrate. The present invention provides a method for forming stacked capacitors, in which a plurality of patterned capacitor outlines, or walls, are formed over the bit line of a semiconductor device. In one aspect of the invention, spacers are formed on the patterned capacitor outlines and become part of the cell poly after being covered with cell nitride. In another aspect, the spacers are formed of a material capable of being etched back, such as titanium nitride. In another aspect, a metal layer is patterned and annealed to a polysilicon layer to form a mask for a capacitor array, and subsequently etched to form the array.

FIELD OF THE INVENTION

[0001] The present invention relates to the field of semiconductorintegrated circuits and, in particular, to capacitor arrays formed overthe bit line of an integrated circuit substrate.

BACKGROUND OF THE INVENTION

[0002] The current semiconductor industry has an ever-increasingpressure for achieving higher device density within a given die area.This is particularly true in memory circuit fabrication, for exampleDynamic Random Access Memory (DRAM) manufacturing. A memory cell of atypical DRAM includes a storage capacitor and a charge transfer fieldeffect transistor. The binary data is stored as electrical charge on thestorage capacitor in the individual memory cell.

[0003] In the early days of DRAM development, planar-type storagecapacitors were used which occupied large substrate areas. These werelater replaced with container capacitors which occupied less surfacearea. Recently, however, with the number of memory cells on the DRAMchip dramatically increasing, the miniaturization of DRAM devicesrequires smaller capacitor features as well as increased storagecapacitance.

[0004] Different approaches have been employed to achieve higher storagecapacitance on a given die area to meet the demands of increasingpacking density. For example, with trench capacitors, electrical chargehas been stored in capacitors formed vertically in a trench thatrequires a deep trench formation, but this encounters significantprocessing difficulties. Another approach is to build a stackedcontainer storage capacitor over at least a portion of the transistor toallow, therefore, smaller cells to be built without losing storagecapacity. Stacked capacitors have become increasingly accepted in thesemiconductor art. However, as the device density continues to increase,the planar surface area required for building the conventional stackedcapacitors must be further reduced. Further, the topography of currentlyfabricated devices requires more difficult planarization processes to beperformed on the DRAM devices.

[0005] Accordingly, there is a need for an improved method forfabricating stacked capacitors that minimizes the drawbacks of the priorart. There is also a need for stacked capacitors which have minimalspacing that is not afforded by current photolithographic feature sizes.

SUMMARY OF THE INVENTION

[0006] The present invention provides a method for forming stackedcapacitors in high density, in which a plurality of patterned capacitoroutlines in the form of walls, are formed over the bit line of asemiconductor device. In one aspect of the invention, spacers are formedon the patterned capacitor walls and become part of the cell polysiliconafter being covered with cell nitride. In another aspect, the spacersare formed of a material capable of being etched back, such as titaniumnitride. In another aspect, a metal layer is patterned and annealed to apolysilicon layer to form a mask for a capacitor array, and subsequentlyetched to form the array.

[0007] Additional features and advantages of the present invention willbe more clearly apparent from the detailed description which is providedin connection with accompanying drawings which illustrate exemplaryembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a diagrammatic sectional view of a semiconductor waferfragment illustrating a base structure for forming the first embodimentof the invention.

[0009]FIG. 2 is a side sectional view of the FIG. 1 semiconductor waferfragment after initial processing steps for forming the first embodimentof the invention.

[0010]FIG. 3 is a side sectional view of the FIG. 2 structure at asubsequent stage of fabrication.

[0011]FIG. 4 is a top view of FIG. 3.

[0012]FIG. 5 is a side sectional view of the FIG. 3 structure at asubsequent stage of fabrication.

[0013]FIG. 6 is a top view of FIG. 5.

[0014]FIG. 7 is side sectional view of the FIG. 5 structure at asubsequent stage of fabrication.

[0015]FIG. 8 is a side sectional view of the FIG. 7 structure at asubsequent stage of fabrication.

[0016]FIG. 9 is a top view of FIG. 8.

[0017]FIG. 10 is a side sectional view of the FIG. 8 structure at asubsequent stage of fabrication.

[0018]FIG. 11 is a side sectional view of the FIG. 10 structure at asubsequent stage of fabrication.

[0019]FIG. 12 is a side sectional view of the FIG. 11 structure at asubsequent stage of fabrication.

[0020]FIG. 13 is a side sectional view of the FIG. 12 structure at asubsequent stage of fabrication.

[0021]FIG. 14 is a side sectional view of the FIG. 13 structure at asubsequent stage of fabrication.

[0022]FIG. 15 is a side sectional view of the FIG. 11 structure at asubsequent stage of fabrication.

[0023]FIG. 16 is a side sectional view of the FIG. 15 structure at asubsequent stage of fabrication.

[0024]FIG. 17 is a side sectional view of the FIG. 16 structure at asubsequent stage of fabrication.

[0025]FIG. 18 is a side sectional view of the FIG. 17 structure at asubsequent stage of fabrication.

[0026]FIG. 19 is a side sectional view of the FIG. 14 structure at asubsequent stage of fabrication.

[0027]FIG. 20 is a diagrammatic sectional view of a semiconductor waferfragment illustrating a base structure for forming another embodiment ofthe invention.

[0028]FIG. 21 is a side sectional view of the FIG. 20 structure at asubsequent stage of fabrication.

[0029]FIG. 22 is a side sectional view of the FIG. 21 structure at asubsequent stage of fabrication.

[0030]FIG. 23 is a side sectional view of the FIG. 22 structure at asubsequent stage of fabrication.

[0031]FIG. 24 is a side sectional view of the FIG. 23 structure at asubsequent stage of fabrication.

[0032]FIG. 25 is a side sectional view of the FIG. 20 structure at asubsequent stage of fabrication.

[0033]FIG. 26 is a diagrammatic sectional view of a semiconductor waferfragment illustrating a base structure for forming another embodiment ofthe invention.

[0034]FIG. 27 is a side sectional view of the FIG. 26 structure at asubsequent stage of fabrication.

[0035]FIG. 28 is top view of FIG. 27.

[0036]FIG. 29 is a side sectional view of the FIG. 27 structure at asubsequent stage of fabrication.

[0037]FIG. 30 is top view of the FIG. 29 structure at a subsequent stageof fabrication.

[0038]FIG. 31 is a side sectional view of the FIG. 29 structure at asubsequent stage of fabrication.

[0039]FIG. 32 is a perspective view of the FIG. 31 structure.

[0040]FIG. 33 is a side sectional view of the FIG. 31 structure at asubsequent stage of fabrication.

[0041]FIG. 34 is a side sectional view of the FIG. 33 structure at asubsequent stage of fabrication.

[0042]FIG. 35 is a side sectional view of the FIG. 34 structure at asubsequent stage of fabrication.

[0043]FIG. 36 is a top view of the FIG. 35 structure.

[0044]FIG. 37 is a side sectional view of the FIG. 35 structure at asubsequent stage of fabrication.

[0045]FIG. 38 is a side sectional view of the FIG. 37 structure at asubsequent stage of fabrication.

[0046]FIG. 39 is a side sectional view of the FIG. 38 structure at asubsequent stage of fabrication.

[0047]FIG. 40 is a side sectional view of the FIG. 39 structure at asubsequent stage of fabrication.

[0048]FIG. 41 is a perspective view of the FIG. 40 structure.

[0049]FIG. 42 is a diagram of a computer system according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0050] In the following detailed description, reference is made tovarious specific embodiments in which the invention may be practiced.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention, and it is to be understoodthat other embodiments may be employed, and that structural andelectrical changes may be made without departing from the spirit orscope of the present invention.

[0051] The term “substrate” used in the following description mayinclude any semiconductor-based structure that has a semiconductorsurface. The term should be understood to include silicon,silicon-on-insulator (SOI), silicon-on-sapphire (SOS),silicon-on-nothing (SON), doped and undoped semiconductors, epitaxiallayers of silicon supported by a base semiconductor foundation, andother semiconductor structures. The semiconductor need not besilicon-based. The semiconductor could be silicon-germanium, germanium,or gallium arsenide. When reference is made to a “substrate” in thefollowing description, previous process steps may have been utilized toform regions or junctions in or on the base semiconductor or foundation.

[0052] Referring now to the drawings, where like elements are designatedby like reference numerals, FIG. 1 depicts a portion of a memory cellconstruction for a DRAM at an intermediate stage of the fabrication, inwhich stacked capacitors are to be formed in accordance with the presentinvention. A pair of memory cell access transistors 33 are formed withinand over a doped well 13 of a substrate 12. The well may be a p-well orn-well depending on the type of transistor 33. The well 13 and the pairof transistors 33 are surrounded by a trench isolation region 14 thatprovides isolation. N-type active regions 16 are provided in the dopedp-type well 13 of substrate 12 (for NMOS transistors) and the pair ofaccess transistors have respective gate stacks 30. The gate stacks 30include an oxide layer 18, a conductive layer 20, such as a dopedpolysilicon layer with tungsten silicide on it, nitride sidewall spacers32, and a nitride cap 22. Additional stacks 31 may also be formed foruse in performing self aligned contact etches to form conductive plugs50, 50 a for capacitor structures in the region between stacks 30, 31.The details of these steps are well-known in the art and are notdescribed in detail herein.

[0053] Polysilicon plugs 50, 50 a (FIG. 1) are formed in a contactopening of a first insulating layer 24, to directly connect to a sourceor drain region 16 of the semiconductor device. The first insulatinglayer 24 could be, for example, borophosphosilicate glass (BPSG),borosilicate glass (BSG), or phosphosilicate glass (PSG). Once thepolysilicon plugs 50, 50 a are formed, the whole structure, includingthe substrate 12 with the gate stacks 30, the first insulating layer 24and the polysilicon plugs 50, 50 a is CMP polished to provide aplanarized surface.

[0054] At this point, a second insulating layer 25, which can be of thesame material as that of the first insulating layer 24, is depositedover the first insulating layer 24 and the polysilicon plugs 50, 50 a. Acontact opening or via is etched over the polysilicon plug 50 a and aconductive layer or inter-connection layer 55 is then deposited andpatterned to connect to polysilicon plug 50 a, as illustrated in FIG. 1.The inter-connection layer 55 functions as a digit line. The digit lineis made of, for example, a polysilicon, titanium nitride, or a tungstenmaterial with a nitride cap.

[0055] Referring now to FIG. 2, a third insulative layer 60 is formedover the inter-connection layer 55. The third insulative layer 60 couldbe, for example, BPSG, BSG, or PSG. The polysilicon plugs 50, that arenot in contact with the digit line 55, are made to extend through thethird insulative layer 60. The contact holes for the polysilicon plugsin layer 60 are made using conventional photolithographic techniques andplasma etching. For example, the etching can be carried out in areactive ion etcher (RIE) using an etchant gas mixture containingfluorine, such as C₅F₈, C₄F₈, CHF₃, CO, O₂, and Ar.

[0056] A layer of conductively doped polysilicon is deposited over layer60 to fill the contact holes and provide conductive plugs 61, andsubsequently etched back to expose layer 60. The conductive plugs 61 areelectrically isolated from the digit line 55, for example, by nitridespacers (not shown). The details of these steps are well-known in theart and other methods may be used.

[0057] Next, an etch stop layer 64 is deposited over the thirdinsulative layer 60. The etch stop layer 64 could be, for example, anitride, or another dielectric etch stop layer. A thick layer 68 ofBPSG, or other insulative material, is then deposited over the etch stoplayer 64. The layer 68 of BPSG is etchably different from the etch stoplayer 64. On top of layer 68, a layer 70 of polysilicon is deposited.Layers 68 and 70 are also substantially etchably different.

[0058] One patterning option for forming capacitors of the presentinvention is to create alternating polysilicon rectangles in thepolysilicon layer 70. This can be accomplished, for example, bypatterning with resist and etching the polysilicon layer 70 to form asquare or rectangular checker board pattern. This etching step etchesthrough the polysilicon layer 70 but stops at the BPSG layer 68. Theresult of this etching step is a checker board pattern of squarepolysilicon blocks 70 c, as illustrated in FIGS. 3 and 4. Alternatively,the patterning can be used to create an alternating pattern ofrectangular shaped blocks, or oval shaped blocks, illustrated by dashedlines 70 d and 70 e, respectively, in FIG. 4.

[0059] Next, sidewall spacers 80 are formed on the sidewalls ofalternating square, rectangular, or oval blocks 70 c, 70 d and 70 e, asshown in FIGS. 5 and 6. The spacers 80 are formed by depositing apolysilicon layer over the polysilicon blocks 70 c, 70 d, or 70 e(hereinafter collectively referred to as “blocks 70 c”), andsubsequently anisotropically etching to provide a plurality of sidewallspacers 80 on all vertical surfaces of alternating blocks 70 c.Collectively, the sidewall spacers 80 and polysilicon blocks 70 c definean array of structure profiles which will be transferred into at leastone of the underlying layers.

[0060] In another patterning option, the square, rectangular, or ovalchecker board pattern of FIGS. 5 and 6 can be printed with photoresistonto the BPSG layer 68. Blocks 70 c and spacers 80 would be comprised ofphotoresist. With this option, the minimum corner to corner spacingbetween the photoresist square or rectangular blocks would have to bemaintained without bridging.

[0061] Next, with reference to FIG. 7, the BPSG layer 68 is selectivelyand anisotropically etched down to the nitride etch stop layer 64 toform BPSG blocks 68 a. Care should be taken during this step to overetchenough to clear the BPSG material out from between the corners of theblocks to prevent possible cell node to cell node shorts. Thepolysilicon spacers 80 and remaining polysilicon blocks 70 c (or 80 and70 c comprised of photoresist) are then selectively removed by suitablemethods such as chemical-mechanical polish (CMP), or wet or dry etching,which are well known in the art.

[0062] Referring now to FIGS. 8 and 9, a spacer 90 is deposited on thevertical walls of the BPSG blocks 68 a. The spacer 90 must be wideenough to bridge together at the corners of BPSG blocks 68 to isolateindividual squares, rectangles, or ovals in order to prevent thepossibility of cell node to cell node shorts. The width W of spacer 90should be greater than distance D of FIG. 6. The spacer 90 material ispreferably either titanium nitride, polysilicon, or another materialetchably different from the BPSG blocks 68 a. The spacer 90 material mayalso comprise platinum. Alternatively, the material for blocks 68 a(material layer 68) can comprise any material that is etchably differentfrom the spacer material 90. The material 68 can be chosen to be amaterial that may remain on the periphery of the integrated circuitwithout the need to remove it during subsequent process steps.

[0063] The BPSG blocks 68 a are then selectively etched away down to thenitride etch stop layer 64, shown in FIG. 10, preferably using a wetetch leaving the spacers 90 intact. The periphery is covered with resistduring this step to prevent removal of BPSG from other areas. At thispoint the spacers 90 are in the form of a square, rectangular, or ovalhoneycomb pattern. Thereafter, as shown in FIG. 11, the etch stop layer64 is selectively etched or otherwise removed using spacers 90 as apattern utilizing techniques well known in the art.

[0064] If the spacer material used for spacers 90 is titanium nitrideand it is desirable to increase its thickness, another layer of titaniumnitride 90 a is deposited over existing spacers 90 and spacer etched, asseen in FIG. 12. Alternatively, titanium nitride can be deposited in onestep in a layer of sufficient thickness approximately equal to layer 90and the two layers 90 a. During this etching process the portions ofnewly deposited titanium nitride spacer 90 a covering the insulativelayer 60 are overetched so as to expose a direct electrical contact withpolysilicon plugs 61.

[0065] Next, with reference to FIG. 13, a hemispherical grain (HSG)polysilicon 92 is deposited over the spacers 90 and 90 a, and exposedpolysilicon plugs 61. This rough polysilicon layer 92 forms the cellnode of a capacitor. The rough HSG layer 92 increases the surface areaof the storage node which improves the cell's capacitance. The upperportion of the HSG layer 92 is then removed by chemical-mechanicalpolish (CMP) or dry etching, as well known in the art, to isolate thetop portion of the titanium nitride layers, designated by referencenumeral 94. The titanium nitride 90, 90 a is then selectively removed byetching with a piranha (sulfuric/hydrogen peroxide) process, or otherselective etch process, to isolate the containers 93 formed by theremaining HSG layer, as shown in FIG. 14. Then, as well known in theart, a cell nitride dielectric and a capacitor upper electrode may bedeposited to form capacitors in the containers 93. For example, asnoted, Hemispherical Grain (HSG) Polysilicon 92 can be deposited to formthe bottom cell plate of the capacitor, followed by deposition of adielectric layer such as a nitride, followed by deposition of an upperelectrode.

[0066] Referring back to FIG. 8, if the spacer material used for spacers90 is polysilicon, then a thin layer of silicon nitride 90 b isdeposited over the polysilicon spacers 90, as shown in FIG. 15. Then,referring to FIG. 16, a layer of polysilicon 90 c is deposited over thesilicone nitride layer 90 b. The polysilicon layer 90 c isanisotropically etched along with the layer of silicon nitride 90 b,etch stop layer 64, and an upper portion of insulating layer 60 todefine containers 91, as shown in FIG. 17. During this etching processthe portions of newly deposited polysilicon layer 90 c covering the etchstop layer 64 are overetched so as to expose a direct electrical contactwith polysilicon plugs 61.

[0067] Hemispherical grain (HSG) polysilicon 92 is then deposited overthe spacers 90, 90 b, and 90 c, and exposed polysilicon plugs 61. Thecontainers 91 are then filled with photoresist and the HSG layer 92 isremoved by chemical-mechanical polish (CMP) or dry etching to expose thehorizontal surfaces of layers 90, 90 b, and 90 c, as shown in FIG. 18.Then, as well known in the art, cell nitride and an upper capacitorelectrode may be deposited to form capacitors in the containers 91, asdiscussed above. During subsequent processing steps, electricalconnections may established between an upper capacitor electrode andpolysilicon spacer 90, to enable the spacer to become part of the cellplate of the capacitor.

[0068] Another way to form capacitors, utilizing the disclosedpatterning techniques, is by utilizing the above disclosed structures ofFIGS. 14 and 18 with barriers, metal electrodes, and cell plates withdielectrics having high dielectric constants. For example, withreference to FIG. 19, a metal insulator silicon (MIS) capacitor can beformed as follows. An ammonia anneal is performed on the wafer tonitridize the surface of the HSG polysilicon 92. Thereafter, if thesidewall spacers 90 (FIGS. 10-14) are titanium nitride spacers, a celldielectric layer 95, such as tantalum pentoxide (Ta₂O₅), is depositedover the polysilicon surface 92. A cell plate of titanium nitride 97 isdeposited over the dielectric layer 95. A layer of polysilicon 99 isthen deposited over layer 97 to prevent oxidation of the titaniumnitride layer 97 during subsequent steps such as deposition of BPSG. Inthe above example, if the sidewall spacers 90 are polysilicon spacers(FIGS. 10, 15-18), then Ta₂O₅ is substituted for silicon nitride inlayer 90 b of FIG. 18.

[0069] Another way of forming capacitors in the present invention is byforming metal insulator metal (MIM) capacitor structures. With referenceto FIG. 20, after conductively doped polysilicon is deposited over layer60 to fill the contact holes and provide conductive plugs 61, thepolysilicon is overetched so that the plugs 61 are recessed below thesurface of the layer 60. A layer of conductive barrier material 101,such as tantalum nitride or tantalum silicon nitride, is deposited overthe layer 60 and subsequently removed by etching or CMP to expose thelayer 60 and the conductive barrier layer 101 on top of the plugs 61.Thereafter, layers 64, 68, and 70 are deposited and patterned asdiscussed above.

[0070] If the sidewall spacers 90 are titanium nitride spacers, theconductive barrier layer 101 is exposed during the etching stepsdescribed above, as shown in FIG. 21. Thereafter, with reference toFIGS. 22 and 23, a layer of platinum 103 is deposited over the titaniumnitride sidewall spacers 90 (or 90 and 90 a). Platinum cell nodes arethen electrically isolated by filling with resist, and the top surfacesof spacers 90 (or 90 and 90 a) are exposed by dry etching, or CMP, toremove the portion of the platinum layer 103 covering the spacers. Then,the spacers 90 (or 90 and 90 a) are removed as described above. Theresist covering the platinum cell nodes is also subsequently removed.The MIM capacitor is formed, with reference to FIG. 24, by depositing adielectric layer 105 having a high dielectric constant, such as Ta₂O₅ orBST, over layer 103. Then a platinum cell plate 107 is deposited overdielectric layer 105. The platinum material in layers 103 and 107 may besubstituted with other suitable materials, for example, ruthenium oxide,rhodium, or platinum rhodium.

[0071] Where the sidewall spacers 90 are not titanium nitride spacers,such as polysilicon sidewall spacers described above, the MIM capacitorsare formed as follows. With reference to FIGS. 15, 16, and 17, asidewall spacer made of platinum is deposited as sidewall spacer 90,instead of a polysilicon spacer. Then, a Ta₂O₅ or barium strontiumtitanate (BST) dielectric, or another high dielectric constantdielectric, is deposited as layer 90 b. A platinum layer is deposited aslayer 90 c. The MIM capacitor structure is then completed as follows.With reference to FIG. 25, a platinum cell node layer 107 is deposited,and the cell nodes are filled with resist. Thereafter, the platinum cellnode layer 107 is etched back to electrically isolate each cellcapacitor, exposing the tops of spacers 90, 90 b, and 90 c, and theresist is removed from the cell nodes.

[0072] The cell node layer 107 is electrically isolated from spacers 90and neighboring cell nodes, as shown in FIG. 25. A Ta₂O₅ cell dielectriclayer 108 is then deposited over cell nodes 107 and exposed spacers 90,90 b, and 90 c. A platinum cell plate 109 is deposited over thedielectric layer 108.

[0073] In subsequent processing steps, cell plate 109 can beelectrically connected to the spacer(s) 90. This can be accomplished,for example, by forming contact holes through layers 108 and 109 to thespacer(s) 90 using a reactive ion etching process, as described above.The contact holes could then be filled with a conductive material toelectrically connect the spacer(s) 90 to the cell plate 109. Theaforementioned connections can be made at the edges of memory arrays,thereby making spacer(s) 90 part of the cell plate of the capacitor.

[0074] In another embodiment of the present invention, the square orrectangular block honeycomb sidewall pattern can be achieved by silicidepatterning. With reference to FIG. 26, a structure is formed accordingto methods well known in the art, and as discussed above, having a digitline 55, and cell node plugs 61, having contacts rising above the digitline 55, in a layer 60, which may be BPSG. A conductive barrier layer101, as shown FIG. 20, may be formed if so required by the resultingcapacitor structure. A layer 164 consisting of nitride is deposited overlayer 60. A thick layer 168 of phosphosilicate glass (PSG) or BPSG isdeposited over layer 164. On top of layer 168 is deposited a layer 170of polysilicon, and a layer 174 of TEOS.

[0075] A layer of patterned photoresist 72 is formed over the TEOS layer174, as shown in FIGS. 27 and 28, to define a first series of trenches74. With reference to FIG. 29, the patterned photoresist 72 is used toetch trenches 175 in the TEOS layer 174. The trenches 175 are etchedover every other row of the cell node polysilicon plugs 61, and theetching is down to and stops at the polysilicon layer 170. Thephotoresist 72 is subsequently removed. As shown in FIG. 30, anotherlayer of patterned photoresist 76 is deposited to define a second seriesof trenches 77 that are perpendicular to the trenches 175 etched intothe TEOS layer 174. Reference numeral 70 a represents rows of the TEOSlayer, beneath the photoresist 76, that have not been etched (covered byphotoresist 72 in the prior etching step). The second series ofphotoresist rows run over every other line of cell node polysiliconplugs 61. The second series of photoresist trenches are used to etchtrenches in polysilicon layer 170 in a two step etch. The first stepetch is a selective anisotropic etch through the exposed polysiliconlayer 170. Then, a selective oxide etch is performed to remove the TEOSlayer 174 from the polysilicon layer 170. This etch is performed downinto the BPSG or PSG layer 168. Therefore, subsequent to etching thesecond row of trenches, remaining portions of the TEOS layer 174 areremoved from the top the polysilicon layer 170 by an oxide etch oranother suitable method, as seen in FIG. 31.

[0076] The effect of etching the two transverse series of trenches isillustrated in FIG. 32, and forms a block checker board pattern. Theresulting structure is comprised of an array of trenches, or analternating square, rectangular, or oval checker pattern having higherelevations of TEOS layer areas 70 c, and intermediate elevations ofpolysilicon 70 b. FIG. 32 also shows the underlying layer of BPSG 168.The alternating square or rectangular checker pattern is comprised ofthree different elevations due to the two separate etching steps: someportions have been etched twice (down to the BPSG layer 168), someportions once, forming areas 70 b, and other portions not etched at all,forming areas 70 c. Alternatively, the aforementioned techniques can beused to form alternating oval structures (not shown). The above stepsused to form the alternating block pattern are discussed in detail inU.S. Pat. No. 6,087,263, the disclosure of which is incorporated hereinby reference.

[0077] Referring now to FIG. 33, a metal layer 178 is deposited over thetop surface of the block pattern. The metal deposited should be one thateasily forms a silicide. An exemplary material for metal layer 178 wouldbe titanium, paladium, or tungsten. A silicide is then formed byannealing the metal layer 178 with the polysilicon layer 170 where thetwo layers are in direct contact.

[0078] Next, with reference to FIG. 34, a wet etch is used to remove theportions of the metal layer 178 that did not react with the polysiliconlayer 170 to form a metal silicide during the annealing step. Theremaining metal portion is the silicide metal layer 180. Any remainingTEOS and polysilicon are subsequently etched away, using any appropriateetching process, thereby leaving behind a silicide block pattern(checker board pattern). The silicide blocks 180 are then isotropicallyetched back so that the silicide blocks do not bridge together at thecorners, as illustrated in FIGS. 35 and 36.

[0079] Using the silicide 180 checkerboard block pattern, as illustratedin FIG. 36, as a mask, the BPSG or PSG layer 168 is then selectively andanisotropically etched down to layer 164 consisting of nitride, oranother suitable dielectric etch stop layer, as shown in FIG. 37.Thereafter, the silicide blocks 180 are removed either by an etchingstep or by a chemical-mechanical polish (CMP), leaving BPSG square orrectangular blocks 168 over layer 164.

[0080] Next, with reference to FIG. 38, a spacer material 182 isdeposited over the blocks 168. The spacer material 182 could be TEOS,amorphous silicon, polysilicon, titanium nitride, or another material.The spacer material 182 will be chosen by the artisan depending upon thetype of capacitor that will be eventually made in the capacitorcontainers defined by the spacer material 182. When choosing spacermaterial 182, consideration must be given to ensure that the spacermaterial 182 is etchably different from the block material 168, therebyenabling subsequent removal of the block material 168 without damagingthe spacer material 182. The spacer material is then spacer etched tocreate sidewall spacers, as illustrated in FIG. 39.

[0081] The BPSG or PSG blocks 168 are then removed by an etchingprocess, or other suitable process, leaving a grid of interlockedspacers 182, as illustrated in FIGS. 40 and 41. The spacers 182 are thencovered with layers of materials depending upon the material chosen forthe spacers, i.e. titanium nitride or polysilicon, as disclosed above.If the spacer 182 is a amorphous silicon spacer, a process of seedingand annealing the spacer can be performed to form a selective HSG layer,prior to the deposition of the cell nitride layer. The HSG layer willprovide the benefit of a greater surface area, resulting in greatercapacitance.

[0082] Thereafter, various types of capacitors can be formed in thecontainers, defined by the interlocked spacers 182, over the burieddigit line 55. For example, Hemispherical Grain (HSG) Polysilicon can bedeposited to form the bottom cell plate of the capacitor, followed by adielectric layer such as a nitride, an then depositing an upperelectrode. As disclosed above, MIS or MIM capacitor structures may alsobe formed.

[0083]FIG. 42 illustrates a computer system 300 that may incorporate thebenefits of the present invention. The system 300 has a memory circuit321 including a capacitor array 320 constructed in accordance with thepresent invention. The system 300 includes a central processing unit(CPU) 302 for performing computer functions, such as executing softwareto perform desired tasks and calculations. One or more input/outputdevices 304, 306, such as a keypad or a mouse, are coupled to the CPU302 and allow an operator to manually input data thereto or to displayor otherwise output data generated by the CPU 302. One or moreperipheral devices such as a floppy disk drive 312 or a CD ROM drive 314may also be coupled to the CPU 302. The computer system 300 alsoincludes a bus 310 that couples the input/output devices 312, 314 andthe memory circuit 321 to the CPU 302.

[0084] While exemplary embodiments of the invention have been describedand illustrated, it should be apparent that many modifications can bemade to the present inventions without departing from its spirit andscope. For example, the above described checker board pattern could beprinted on BPSG, PSG, or another layer, utilizing photoresistpatterning, or other patterning techniques. Accordingly the invention isnot limited by the foregoing description or drawings, but is onlylimited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of forming a semiconductor memorystructure comprising: forming a capacitor support structure over a digitline and over a substrate, said support structure includinginterconnected sidewalls defining containers between said sidewalls, atleast some of said containers being formed over respective capacitorplugs; and forming capacitors in at least some of said containers. 2.The method according to claim 1 wherein said capacitor plugs extend to atransistor region formed in said substrate.
 3. The method according toclaim 1 wherein said support structure comprises a single layer ofmaterial.
 4. The method according to claim 1 wherein said supportstructure comprises a plurality of layers of material.
 5. The methodaccording to claim 1 further comprising forming said support structureby etching at least one layer of the support structure forming materialto form one of rectangular, oval, and square alternating block pattern.6. The method according to claim 5 further comprising forming sidewallspacers on vertical surfaces of said block pattern.
 7. The methodaccording to claim 5 further comprising transferring said block patterninto an underlying layer of said support structure forming material. 8.The method according to claim 7 further comprising forming sidewallspacers on sidewalls of said transferred block pattern.
 9. The methodaccording to claim 8 further comprising forming said capacitor supportstructure from said sidewall spacers.
 10. The method according to claim5 further comprising forming a metal layer on top of said alternatingblock pattern.
 11. The method according to claim 10 wherein said metallayer consists of one of titanium, palladium, and tungsten.
 12. Themethod according to claim 10 further comprising annealing said metallayer to form a silicide.
 13. The method according to claim 5 whereinsaid support structure forming material comprises a BPSG layer between anitride layer and a polysilicon layer.
 14. The method according to claim5 wherein said support structure forming material comprises a nitridelayer beneath a BPSG layer, a polysilicon layer over said BPSG layer,and a TEOS layer over said polysilicon layer.
 15. The method accordingto claim 5 wherein said support structure forming material comprises anitride layer beneath a BPSG or PSG layer, a polysilicon layer over saidBPSG layer, and a TEOS layer over said polysilicon layer.
 16. The methodaccording to claim 8 wherein said sidewall spacers comprise polysiliconspacers.
 17. The method according to claim 8 wherein said sidewallspacers comprise titanium nitride spacers.
 18. The method according toclaim 8 wherein said sidewall spacers comprise TEOS spacers that areetched from between the capacitors.
 19. The method according to claim 8wherein said sidewall spacers comprise platinum spacers.
 20. The methodaccording to claim 8 wherein said sidewall spacers comprise amorphoussilicon spacers.
 21. The method according to claim 20 further comprisingseeding and annealing said spacers to form an HSG layer.
 22. The methodaccording to claim 1 wherein said capacitors are formed as metalinsulator metal capacitors.
 23. The method according to claim 22 whereinsaid capacitors comprise a first platinum layer, a Ta₂O₅ or BST layer,and a second platinum layer.
 24. The method according to claim 23further comprising forming a conductive barrier layer beneath either thefirst or second platinum layer.
 25. The method according to claim 24wherein said conductive barrier layer comprises tantalum nitride ortantalum silicon nitride.
 26. The method according to claim 1 whereinsaid capacitors are formed as metal insulator silicon capacitors. 27.The method according to claim 26 wherein said capacitors comprise an HSGlayer, a Ta₂O₅ layer, and a titanium nitride layer.
 28. The methodaccording to claim 8 wherein said spacers are electrically connected toa cell plate and function as part of the cell plate of the capacitor.29. A method of forming a capacitor array comprising: forming a digitline over a substrate, providing electrical contacts extending abovesaid digit line, forming a pattern of interconnected sidewalls over saidelectrical contacts, and forming capacitors electrically connected tosaid electrical contacts in containers defined by said sidewalls. 30.The method according to claim 29 wherein said electrical contacts extendto a transistor region formed in said substrate.
 31. The methodaccording to claim 29 further comprising forming said interconnectedsidewalls in a support structure.
 32. The method according to claim 31wherein said support structure comprises a single layer of material. 33.The method according to claim 31 wherein said support structurecomprises a plurality of layers of material.
 34. The method according toclaim 31 further comprising forming an alternating block pattern in atleast one layer of material in said support structure.
 35. The methodaccording to claim 34 further comprising forming sidewall spacers onvertical surfaces of said block pattern.
 36. The method according toclaim 34 further comprising transferring said block pattern into anunderlying layer of said support structure.
 37. The method according toclaim 36 further comprising forming sidewall spacers on said transferredblock pattern.
 38. The method according to claim 37 further comprisingforming said interconnected sidewalls from said sidewall spacers. 39.The method according to claim 34 further comprising forming a metallayer on top of said alternating block pattern.
 40. The method accordingto claim 39 wherein said metal layer consists of one of titanium,palladium, and tungsten.
 41. The method according to claim 33 furthercomprising annealing said metal layer to form a silicide.
 42. The methodaccording to claim 33 wherein said plurality of layers comprises a BPSGlayer between a nitride layer and a polysilicon layer.
 43. The methodaccording to claim 33 wherein said plurality of layers comprises anitride layer beneath a BPSG layer, a polysilicon layer over said BPSGlayer, and a TEOS layer over said polysilicon layer.
 44. (Amended) Themethod according to claim 33 wherein said plurality of layers comprisesa nitride layer beneath a PSG layer, a polysilicon layer over said PSGlayer, and a TEOS layer over said polysilicon layer.
 45. The methodaccording to claim 37 wherein said sidewall spacers comprise polysiliconspacers.
 46. The method according to claim 37 wherein said sidewallspacers comprise titanium nitride spacers.
 47. The method according toclaim 37 wherein said sidewall spacers comprise TEOS spacers that areetched from between the capacitors.
 48. The method according to claim 37wherein said sidewall spacers comprise platinum spacers.
 49. The methodaccording to claim 37 wherein said sidewall spacers comprise amorphoussilicon spacers.
 50. The method according to claim 43 further comprisingseeding and annealing said spacers to form an HSG layer.
 51. The methodaccording to claim 29 wherein said capacitors are formed as metalinsulator metal capacitors.
 52. The method according to claim 51 whereinsaid capacitors comprise a first platinum layer, a Ta₂O₅ or BST layer,and a second platinum layer.
 53. The method according to claim 52further comprising forming a conductive barrier layer beneath either thefirst or second platinum layer.
 54. The method according to claim 53wherein said conductive barrier layer comprises tantalum nitride ortantalum silicon nitride.
 55. The method according to claim 29 whereinsaid capacitors are formed as metal insulator silicon capacitors. 56.The method according to claim 55 wherein said capacitors comprise an HSGlayer, a Ta₂O₅ layer, and a titanium nitride layer.
 57. The methodaccording to claim 37 wherein said spacers are electrically connected toa cell plate and function as part of the cell plate of the capacitor.58. A method of forming integrated circuitry comprising: providing atransistor array over a substrate; providing a digit line over saidtransistor array; providing a plurality of layers of material over saiddigit line; forming one of square, rectangular, and oval pattern in atleast one of said plurality of layers of material, said pattern beingdefined by having raised structures alternating with recesses;transferring said pattern into an underlying layer in said plurality oflayers; forming sidewall spacers on vertical surfaces of saidtransferred pattern; and forming a capacitor container array defined bysaid sidewall spacers.
 59. The method according to claim 58 furthercomprising forming capacitors in said containers.
 60. The methodaccording to claim 58 further comprising forming cell node polysiliconplugs extending above said digit line.
 61. The method according to claim58 further comprising etching only the top layer of said plurality oflayers of material to from said pattern.
 62. The method according toclaim 58 further comprising etching two or more of said plurality oflayers of material to form said pattern.
 63. The method according toclaim 58 further comprising forming a metal layer on top of saidpattern.
 64. The method according to claim 63 wherein said metal layerconsists of one of titanium, palladium, and tungsten.
 65. The methodaccording to claim 63 further comprising annealing said metal layer toform a silicide.
 66. The method according to claim 58 wherein saidplurality of layers of material comprises a BPSG layer between apolysilicon layer and a nitride layer.
 67. The method according to claim58 wherein said plurality of layers of material comprises a nitridelayer beneath a BPSG layer, a polysilicon layer over said BPSG layer,and a TEOS layer over said polysilicon layer.
 68. The method accordingto claim 58 wherein said plurality of layers of material comprises anitride layer beneath one of a PSG and a BPSG layer, a polysilicon layerover said one of BPSG and PSG layer, and a TEOS layer over saidpolysilicon layer.
 69. The method according to claim 58 wherein saidsidewall spacers comprise polysilicon spacers.
 70. The method accordingto claim 58 wherein said sidewall spacers comprise titanium nitridespacers.
 71. The method according to claim 58 wherein said sidewallspacers comprise TEOS spacers that are etched from between thecapacitors.
 72. The method according to claim 58 wherein said sidewallspacers comprise platinum spacers.
 73. The method according to claim 58wherein said sidewall spacers comprise amorphous silicon spacers. 74.The method according to claim 73 further comprising seeding andannealing said spacers to form an HSG layer.
 75. The method according toclaim 58 wherein said capacitors are formed as metal insulator metalcapacitors.
 76. The method according to claim 75 wherein said capacitorscomprise a first platinum layer, a Ta₂O₅ or BST layer, and a secondplatinum layer.
 77. The method according to claim 76 further comprisingforming a conductive barrier layer beneath either the first or secondplatinum layer.
 78. The method according to claim 77 wherein saidconductive barrier layer comprises tantalum nitride or tantalum siliconnitride.
 79. The method according to claim 58 wherein said capacitorsare formed as metal insulator silicon capacitors.
 80. The methodaccording to claim 79 wherein said capacitors comprise an HSG layer, aTa₂O₅ layer, and a titanium nitride layer.
 81. The method according toclaim 58 wherein said spacers are electrically connected to a cell plateand function as part of the cell plate of the capacitor.
 82. Anintegrated circuit comprising: a substrate; a digit line over saidsubstrate; an array of interconnected sidewalls over said digit line,said interconnected sidewalls defining capacitor formation regions, anda plurality of capacitors respectively formed in at least some of saidcapacitor formation regions.
 83. The circuit according to claim 82wherein said sidewalls comprise polysilicon sidewalls.
 84. The circuitaccording to claim 82 wherein said sidewalls comprise titanium nitridesidewalls.
 85. The circuit according to claim 82 wherein said sidewallscomprise platinum spacers.
 86. The circuit according to claim 82 whereinsaid sidewalls comprise TEOS sidewalls that are etched from between thecapacitors.
 87. The circuit according to claim 82 wherein saidcapacitors are comprised of a nitride layer deposited between an HSGlayer and another electrode layer.
 88. The circuit according to claim 82wherein said sidewalls comprise amorphous silicon sidewalls.
 89. Thecircuit according to claim 88 further comprising seeding and annealingsaid sidewalls to form an HSG layer.
 90. The circuit according to claim82 wherein said capacitors are formed as metal insulator metalcapacitors.
 91. The circuit according to claim 90 wherein saidcapacitors comprise a first platinum layer, a Ta₂O₅ or BST layer, and asecond platinum layer.
 92. The circuit according to claim 91 furthercomprising forming a conductive barrier layer beneath either the firstor second platinum layer.
 93. The circuit to claim 92 wherein saidconductive barrier layer comprises tantalum nitride or tantalum siliconnitride.
 94. The circuit according to claim 82 wherein said capacitorsare formed as metal insulator silicon capacitors.
 95. The circuitaccording to claim 94 wherein said capacitors comprise an HSG layer, aTa₂O₅ layer, and a titanium nitride layer.
 96. The circuit according toclaim 8 wherein said sidewalls are electrically connected to a cellplate and function as part of the cell plate of the capacitor.
 97. Acomputer system comprising: a processor; and a memory device comprisingan array of interconnected sidewalls over a digit line, saidinterconnected sidewalls defining capacitor formation regions, and aplurality of capacitors respectively formed in at least some of saidcapacitor formation regions.
 98. The system according to claim 97wherein said sidewalls comprise polysilicon sidewalls.
 99. The systemaccording to claim 97 wherein said sidewalls comprise platinumsidewalls.
 100. The system according to claim 97 wherein said sidewallscomprise titanium nitride sidewalls.
 101. The system according to claim97 wherein said sidewalls comprise TEOS sidewalls that are etched frombetween the capacitors.
 102. The system according to claim 97 whereinsaid capacitors are comprised of a nitride layer deposited between anHSG layer and another electrode layer.
 103. The system according toclaim 97 wherein said sidewalls comprise amorphous silicon sidewalls.104. The system according to claim 97 wherein said sidewalls compriseHSG sidewalls.
 105. The system according to claim 97 wherein saidcapacitors are formed as metal insulator metal capacitors.
 106. Thesystem according to claim 105 wherein said capacitors comprise a firstplatinum layer, a Ta₂O₅ or BST layer, and a second platinum layer. 107.The system according to claim 106 further comprising forming aconductive barrier layer beneath either the first or second platinumlayer.
 108. The system according to claim 107 wherein said conductivebarrier layer comprises tantalum nitride or tantalum silicon nitride.109. The system according to claim 97 wherein said capacitors are formedas metal insulator silicon capacitors.
 110. The system according toclaim 109 wherein said capacitors comprise an HSG layer, a Ta₂O₅ layer,and a titanium nitride layer.
 111. The system according to claim 97wherein said sidewalls are electrically connected to a cell plate andfunction as part of the cell plate of the capacitors.
 112. The methodaccording to claim 6 wherein said sidewall spacers comprise TEOS spacersand are left between said capacitors.
 113. The method according to claim37 wherein said sidewall spacers comprise TEOS spacers and are leftbetween said capacitors.
 114. The method according to claim 58 whereinsaid sidewall spacers comprise TEOS spacers and are left between saidcapacitors.
 115. The circuit according to claim 82 wherein saidsidewalls comprise TEOS sidewalls which are left between saidcapacitors.
 116. The system according to claim 97 wherein said sidewallscomprise TEOS sidewalls which are left between said capacitors.